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12 - /14 - bit high bandwidth multiplying dacs with serial interface data sheet ad5444 / ad5446 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other ri ghts of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and re gistered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures 12 mhz multiplying bandwidth inl of 0.5 lsb at 12 bit s pin - com patible 12 - /14 - bit current output dac 2.5 v to 5.5 v supply operation 10- lead msop package 10 v reference input 50 mhz serial interface 2.7 msps update rate extended temperature rang e: ?40c to +125c 4 - quadrant multiplication power - on reset with brownout detection 0.4 a typical current consumption guaranteed monotonic applications portable , battery - powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming automotive radar general description the ad5444/ad5446 1 are cmos 12 - bit and 14 - bit, current output , digital - to - an alog converters (dacs) . operating from a single 2.5 v to 5.5 v power supply, these devices are suited for battery - powered and other applications. as a result of the cmos submi cron manufacturing process, these part s offer excel lent 4 - quadrant multiplication char - acteristics of up to 12 mhz. these dacs use a double - buffered, 3 - wire serial interface that is compatible with spi?, qspi?, microwire?, and most dsp interface standards. on power - up, the internal shift register and latc hes are filled with 0s, and the dac output is at zero scale. the applied external reference input voltage (v ref ) determines the full - scale output current. these parts can handle 10 v inputs on the reference , despite operating from a single - supply power s upply of 2.5 v to 5.5 v. an integrated feedback resistor (r fb ) provides temperature tracking and full - scale voltage outpu t when combined with an external current - to - voltage precision amplifier. the ad5444/ad5446 dacs are available in small 10- lead msop pa ckages , which are pin - compatible with the ad5425 / ad5426 / ad5432 / ad5443 fa mily of dacs. the ev - ad5443/46/53sdz board is available for evaluating dac performance. for more information, see the ug - 327 e valuation b oard u ser g uide. 1 us patent number 5,689,2 57. functional block diagram 04588-001 power-on reset gnd v ref r fb i out 1 i out 2 r sdo contro l logic and input shift register dac register 12-bit r-2r dac input l a tch sclk sdin sync v dd ad5444/ ad5446 figure 1.
ad5444/ad5446 data sheet rev. e | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 14 ? general description ....................................................................... 15 ? dac section ................................................................................ 15 ? circuit operation ....................................................................... 15 ? single-supply applications ....................................................... 17 ? adding gain ................................................................................ 17 ? divider or programmable gain element ................................ 17 ? amplifier selection .................................................................... 18 ? reference selection .................................................................... 18 ? serial interface ................................................................................ 20 ? microprocessor interfacing ....................................................... 21 ? pcb layout and power supply decoupling ................................ 23 ? overview of ad54xx and ad55xx current output devices ... 24 ? outline dimensions ....................................................................... 25 ? ordering guide .......................................................................... 25 ? revision history 6/13rev. d to rev. e changes to general description section ...................................... 1 change to figure 46 and figure 47 .............................................. 21 changes to ordering guide .......................................................... 25 4/12rev. c to rev. d changes to general description section ...................................... 1 deleted evaluation board for the dac section ......................... 23 deleted power supplies for the evaluation board section ....... 23 deleted figure 54; renumbered sequentially ............................ 24 deleted figure 55 and figure 56 ................................................... 25 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 25 deleted figure 57 ............................................................................ 26 4/07rev. b to rev. c changes to table 9 .......................................................................... 19 changes to ordering guide .......................................................... 28 changes to features .......................................................................... 1 changes to general description .................................................... 1 changes to table 1 ............................................................................ 3 changes to figure 22 ...................................................................... 10 changes to figure 23 ...................................................................... 10 changes to table 9 .......................................................................... 19 changes to table 12 ........................................................................ 27 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 28 4/05rev. 0 to rev. a added ad5446 ................................................................... universal changes to features .......................................................................... 1 changes to general description ..................................................... 1 changes to specifications ................................................................. 3 inserted figure 7; renumbered sequentially ................................. 9 inserted figure 9; renumbered sequentially ................................. 9 inserted figure 13; renumbered sequentially ........................... 10 changes to figure 22 ...................................................................... 11 changes to figure 23 ...................................................................... 11 changes to serial interface ............................................................ 20 changes to figure 44 ...................................................................... 20 changes to figure 45 ...................................................................... 20 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 28 10/04revision 0: initial version
data sheet ad5444/ad5446 rev. e | page 3 of 28 specifications v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v. temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance measured with op177, and ac performance measured with ad8038, unless otherwise noted. table 1 . parameter min typ max unit conditions s tatic performance ad5444 resolution 12 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic total unadjusted error (tue) 1 lsb gain error 0.5 lsb ad5446 resolution 14 bit s relative accuracy 2 lsb differential nonlinearity ? 1/+2 lsb guaranteed monotonic total unadjusted error (tue) 4 lsb gain error 2.5 lsb gain error t emp erature coefficient 1 2 ppm fsr/c output leakage current 1 na data = 0x0000, t a = 25c, i out 1 10 na data = 0x0000, t a = ?40 c to +125c, i out 1 reference input 1 reference input range 10 v v ref input resistance 7 9 11 k? input resistance t c = ?50 ppm/c r fb feedback resistance 7 9 11 k? input resistance t c = ?50 ppm/c input capacitance zero - scale code 18 22 pf full - scale code 18 22 pf digital inputs/outputs 1 input high voltage, v ih 2.0 v v dd = 3.6 v to 5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage , v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 na t a = 25c 10 na t a = ?40c to +125c input capacitance 10 pf
ad5444/ad5446 data sheet rev. e | page 4 of 28 parameter min typ max unit conditions dynamic performance 1 reference multiplying b andwidth 12 mhz v ref = 3.5 v, dac loaded with all 1s multiplyin g feedthrough error v ref = 3.5 v , dac loaded with all 0s 72 db 100 k hz 64 db 1 mhz 44 db 10 mhz output voltage settling time v ref = 10 v, r load = 100 ?, dac latch alternately loaded with 0s and 1s measured to 1 mv of fs 100 110 ns measured to 4 mv of fs 24 40 ns measured to 16 mv of fs 16 33 ns digital delay 20 40 ns interface delay time 10% -to - 90% settling time 10 30 ns rise and fall time, v ref = 10 v, r load = 100 ? digital -to - analog glitch impulse 2 nv -s 1 lsb change around major carry, v ref = 0 v output capacitance i out 1 13 pf dac latches loaded with all 0s 28 pf dac latches loaded with all 1s i out 2 18 pf dac latches loaded with all 0s 5 pf dac latches loaded with all 1s digital feedthrough 0.5 nv -s feedthrough to dac output with cs high and alternate loading of all 0s and all 1s analog thd 83 db v ref = 3.5 v p - p, all 1s loaded, f = 1 khz digital thd clock = 1 mhz, v ref = 3.5 v 50 khz f ou t 71 db 20 khz f out 77 db output noise spectral density 25 nv/hz @ 1 khz sfdr performance (wide b and) clock = 10 mhz, v ref = 3.5 v 50 khz f out 78 db 20 khz f out 74 db sfdr performance (narrow band) clock = 1 mhz, v ref = 3.5 v 50 khz f out 87 db 20 khz f out 85 db intermodulation distortion 79 db f 1 = 20 khz, f 2 = 25 khz, c lock = 1 mhz, v ref = 3.5 v power requirements power supply range , v dd 2.5 5.5 v supply current , i dd 0.4 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd 0.6 a t a = 25c, logic inputs = 0 v or v dd power supply sensitivity 1 0.001 %/% ?v dd = 5% 1 guaranteed by design and characteri zation; not subject to production test .
data sheet ad5444/ad5446 rev. e | page 5 of 28 timing characteristics all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v, temperature range for y version: ?40c to +125c; all specifications t min to t max , unless otherwise noted. table 2. parameter 1 v dd = 4.5 v to 5.5 v v dd = 2.5 v to 5.5 v unit conditions/comments f sclk 50 50 mhz max maximum clock frequency. t 1 20 20 ns min sclk cycle time. t 2 8 8 ns min sclk high time. t 3 8 8 ns min sclk low time. t 4 8 8 ns min sync falling edge to sclk active edge setup time. t 5 5 5 ns min data setup time. t 6 4.5 4.5 ns min data hold time. t 7 5 5 ns min sync rising edge to sclk active edge setup time t 8 30 30 ns min minimum sync high time. t 9 23 30 ns min sclk active edge to sdo valid. update rate 2.7 2.7 msps consists of cycle time, sync high time, data setup time and output voltage settling time. 1 guaranteed by design and characterization; not subject to production test. 0 4588-002 t 7 t 1 t 3 t 2 t 4 t 5 t 6 db15 db0 sclk sync sdin t 8 figure 2. standalone timing diagram db15 (n) db0 (n) db15 (n + 1) db0 (n + 1) sclk sdin sdo notes alternatively, data can be clocked into input shift register on rising edge of sclk as determined by control bits. in this case, data is clocked out of sdo on falling edge of sclk. timing as above, with sclk inverted. t 4 t 5 t 6 t 2 t 1 t 3 t 7 t 8 t 9 db15 (n) db0 (n) s ync 04588-003 figure 3. daisy-chain timing diagram
ad5444/ad5446 data sheet rev. e | page 6 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up. table 3 . parameter r ating v dd to gnd ? 0.3 v to +7 v v ref , r fb to gnd ? 12 v to +12 v i out 1, i out 2 to gnd ? 0.3 v to +7 v logic inputs and outputs 1 ? 0.3 v to v dd + 0.3 v input current (all pin s except supplies ) 10 ma operating temperature range ? 40c to +125c extended ( y version) storage temperature range ? 65c to +150c junction temperature 150c 10- lead msop ja thermal impedance 206c/w lead temperature, soldering (10 s ec ) 300c ir reflow, peak temperature (<20 s ec ) 235c 1 overvoltage s at sclk, sync , and s din are clamped by internal diodes . stresses above those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. i o l 200 a to output pin 200 a i oh c l 20pf v oh (min) +v o l (max) 2 04588-004 figure 4 . load circuit for sdo timing specifications esd caution
data sheet ad5444/ad5446 rev. e | page 7 of 28 pin configuration an d function descripti ons 04588-005 10 9 8 7 6 1 2 3 4 5 i out 1 i out 2 gnd sclk sdin r fb v ref v dd sdo ad5444/ ad5446 t o p view (not to scale) sync figure 5 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 i out 1 dac current output. 2 i out 2 dac analog ground. thi s pin should normally be tied to the analog ground of the system. 3 gnd ground pin. 4 sclk serial clock input. by default, data is clocked into the input shift register on the falling edge of the serial clock input. alternatively, by means of the s erial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of sclk. 5 sdin serial data input. data is clocked into the 16 - bit input register on the active edge of the serial clock input. by defa ult on power - up, data is clocked into the shift register on the falling edge of sclk. the control bits allow the user to change the active edge to the rising edge. 6 sync active low control input. this is the frame synchronization signal for the input data. when sync is taken low, data is loaded to the shift register on the active edge of the following clocks. the output updates on the rising edge of sync . 7 sdo serial data output. t his pin allows a number of parts to be daisy - chained. by default, data is clocked into the shift register on the falling edge and out via sdo on the rising edge of sclk. data is always clocked out on the alternate edge to data loaded to the shift register. 8 v dd positive power supply input. this part can be operated from a supply of 2.5 v to 5.5 v. 9 v ref dac reference voltage input. 10 r fb dac feedback resistor. establishes voltage output for the dac by connecting to an external amplifier outpu t.
ad5444/ad5446 data sheet rev. e | page 8 of 28 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 512 1024 1536 2048 2560 3072 3584 4096 code inl (lsb) t a = 25c v ref = 10v v dd = 5v 04588-006 figure 6 . inl vs. code (12- b it dac) 2.0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 0 2048 4096 6144 8192 10240 12288 14336 16384 04588-076 code in l (lsb) t a = 25c v ref = 10v v dd = 5v figure 7 . inl vs. code (14- bit dac) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 code dnl (lsb) t a = 25c v ref = 10v v dd = 5v 04588-008 figure 8 . dnl vs. code (12 - bit dac) 2.0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 0 2048 4096 6144 8192 10240 12288 14336 16384 04588-077 code dn l (lsb) t a = 25c v ref = 10v v dd = 5v figure 9 . dnl vs. code (14 - bit dac) ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 2 3 4 5 6 7 8 9 10 reference vo lt age (v) in l (lsb) t a = 25c v dd = 5v ad5444 04588-047 max in l min in l figure 10 . inl vs. reference voltage ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2 3 4 5 6 7 8 9 10 reference vo lt age (v) dn l (lsb) t a = 25c v dd = 5v ad5444 04588-048 max dn l min dn l figure 11 . dnl vs. reference voltage
data sheet ad5444/ad5446 rev. e | page 9 of 28 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 code tue (lsb) t a = 25c v ref = 10v v dd = 5v 04588-013 figure 12 . tue vs. code (12 - bit dac) 2.0 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 0 2048 4096 6144 8192 10240 12288 14336 16384 04588-078 code in l (lsb) t a = 25c v ref = 10v v dd = 5v figure 13 . tue vs. code (14 - bit dac) ?2.0 ?1.5 ?1.0 0 1.0 1.5 2.0 2 3 4 5 8 9 10 reference vo lt age (v) tue (lsb) 04588-052 7 6 max tue ?0.5 0.5 t a = 25c v dd = 5v ad5444 min tue figure 14 . tue vs. reference voltage ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?60 ?40 ?20 0 60 80 100 120 140 temper a ture (c) gain error (lsb) v ref = 10v 04588-049 40 20 v dd = 5v v dd = 3v figure 15 . gain error vs. temperature ?2.0 ?1.5 ?1.0 0 1.0 1.5 2.0 2 3 4 5 8 9 10 reference vo lt age (v) gain error (lsb) 04588-051 7 6 ?0.5 0.5 t a = 25c v dd = 5v ad5444 figure 16 . gain error vs. reference vol tage i out 1, v dd = 3v i out 1, v dd = 5v ?40 ?20 0 20 40 60 80 100 120 temperature (c) 2.0 1.6 1.2 0.8 0.4 0 i out 1 leakage (na) 04588-017 figure 17 . i out 1 leakage current vs. temperature
ad5444/ad5446 data sheet rev. e | page 10 of 28 0 1 2 3 4 5 input voltage (v) 2.5 2.0 1.5 1.0 0.5 0 supply current (ma) t a = 25c 04588-018 v dd = 5v v dd = 3v figure 18 . supply current vs. logic input voltage all 1s all 0s 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 supply current (a) ?40 ?20 0 20 40 60 80 100 120 temperature (c) v dd = 5v v dd = 3v 04588-019 figure 19 . supply current vs. temperature 04588-055 1 10 100 1k 10k 100k 1m 10m frequenc y (hz) 6 0 1 2 3 4 5 supp l y current (ma) t a = 25c ad5444 loading 0101 0101 0101 v dd = 5v v dd = 3v figure 20 . supply current vs . update rate 2.5 5.5 supp l y vo lt age (v) 1.8 1.2 1.0 0.4 0.2 0 v ih 04588-053 1.6 1.4 0.8 0.6 3.0 3.5 4.5 4.0 5.0 v il threshold vo lt age (v) t a = 25 c figure 21 . threshold voltage vs. supply voltage 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m 100m gain (db) frequency (hz) 04588-083 all on db11 db10 db9 db8 db6 db5 db4 db3 db7 db2 db12 db13 v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier t a = 25c loading zs to fs figure 22 . reference multiplying bandwidth vs. frequenc y and code 0.6 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 10k 100k 1m 10m 100m gain (db) frequency (hz) 04588-084 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf ad8038 amplifier figure 23 . reference multiplying bandwidth vs. frequency all 1s loaded
data sheet ad5444/ad5446 rev. e | page 11 of 28 04588-057 10k 100k 1m 10m 100m frequenc y (hz) 3 ?9 0 gain (db) t a = 25c v dd = 5v ?6 ?3 v ref = 2 v , ad8038 c comp = 1pf v ref = 2 v , ad8038 c comp = 1.5pf v ref = 15 v , ad8038 c comp = 1pf v ref = 15 v , ad8038 c comp = 1.5pf v ref = 15 v , ad8038 c comp = 1.8pf figure 24 . reference multiplying bandwidth vs. frequency and compensation capacitor 04588-058 50 200 225 250 time (ns) 0.08 ?0.06 output vo lt age (v) ?0.02 175 100 125 150 75 0.06 0.04 0.02 0 ?0.04 t a = 25 c v ref = 0v ad8038 am p c comp = 1.8pf v dd = 5 v 0x7ff t o 0x800 nrg = 2.154n v -s v dd = 3v 0x7ff t o 0x800 nrg = 1.794n v -s v dd = 5 v 0x800 t o 0x7ff nrg = 0.694n v -s v dd = 5 v 0x800 t o 0x7ff nrg = 0.694n v -s figure 25 . midscale transition, v ref = 0 v 50 200 225 250 time (ns) ?1.66 ?1.80 output vo lt age (v) ?1.76 175 100 125 150 75 ?1.68 ?1.70 ?1.72 ?1.74 ?1.78 t a = 25 c v ref = 3.5v ad8038 am p c comp = 1.8pf v dd = 5 v 0x7ff t o 0x800 nrg = 2.154n v -s v dd = 3v 0x7ff t o 0x800 nrg = 1.794n v -s v dd = 5 v 0x800 t o 0x7ff nrg = 0.694n v -s v dd = 5 v 0x800 t o 0x7ff nrg = 0.694n v -s 04588-059 fig ure 26 . midscale transition, v ref = 3.5 v 04588-060 1 10 100 1k 10k 100k 1m 10m frequenc y (hz) 10 ?100 ?90 ?70 ?50 ?30 ?10 psrr (db) t a = 25c v dd = 3v ad8038 amplifier ?80 ?60 ?40 ?20 0 ful l scale zero scale figure 27 . power supply rejection ratio vs. frequency 04588-061 thd + n (db) t a = 25 c v dd = 5v v ref = 3.5v 100 1k 10k 100k frequenc y (hz) ?60 ?90 ?85 ?75 ?65 ?80 ?70 figure 28 . thd + noise vs. frequency 04588-062 0 50 f out (khz) 100 0 sfdr (db) 40 20 30 40 10 80 60 20 t a = 25 c v ref = 3.5v ad8038 am p mclk = 500khz mclk = 1mhz mclk = 200khz figure 29 . wideband sfdr vs. f out frequency
ad5444/ad5446 data sheet rev. e | page 12 of 28 ?120 ?100 ?80 ?60 ?40 ?20 0 0 500k t a = 25 c v dd = 5v v ref = 3.5v ad8038 am p frequenc y (hz) 400k 300k 200k 100k sfdr (db) 04588-063 figure 30 . wideband sfdr , f out = 20 khz, clock = 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 500k t a = 25 c v dd = 5v v ref = 3.5v ad8038 am p frequenc y (hz) 400k 300k 200k 100k sfdr (db) 04588-064 figure 31 . wideband sfdr, f out = 50 khz, clock = 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 10k 30k t a = 25 c v dd = 5v v ref = 3.5v ad8038 am p frequenc y (hz) 25k 20k 15k sfdr (db) 04588-065 figure 32 . narrow - band sf dr, f out = 20 khz, clock = 1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 30k 70k t a = 25 c v dd = 5v v ref = 3.5v ad8038 am p frequenc y (hz) 60k 50k 40k sfdr (db) 04588-066 figure 33 . narrow - band sfdr , f out = 50 khz, clock = 1 mhz
data sheet ad5444/ad5446 rev. e | page 13 of 28 ?100 ?90 ?80 ?60 ?40 ?20 0 10k 35k t a = 25 c v ref = 3.5v ad8038 am p frequenc y (hz) 30k 25k 20k 15k imd (db) 04588-067 ?70 ?50 ?30 ?10 figure 34 . narrow - band imd , f out = 20 khz and 25 khz, clock = 1 mhz ?100 ?90 ?80 ?60 ?40 ?20 0 0 500k t a = 25 c v ref = 3.5v ad8038 am p frequenc y (hz) 400k 300k 200k 100k imd (db) 04588-068 ?70 ?50 ?30 ?10 figure 35 . wideband imd , f out = 20 khz and 25 khz, clock = 1 mhz 04588-069 100 1k 10k 100k 1m frequenc y (hz) 80 0 70 output noise (nv/ hz) t a = 25 c ad8038 am p 50 60 40 20 30 10 ful l scale loaded t o dac midscale loaded t o dac zero scale loaded t o dac figure 36 . output noise spectral density
ad5444/ad5446 data sheet rev. e | page 14 of 28 terminology relative accura cy or integral nonlinearity relative accuracy or integral nonlinearity is a measure of the maximum deviation from a st raight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero scale and full scale and is normally expressed in lsbs or as a percentage of full - scale reading. differential nonlinearity d ifferential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error gain error or full - scale error is a measure of the output error between an ideal dac and the actual device output. for this dac, ideal maximum output is v ref ? 1 lsb. gain error of the dac is adjustable to zero with external resistance. output leakage curr ent output leakage current is current that flows in the dac ladder switches when the ladder is turned off. for the i out 1 line , it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current flows in the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time the amount of time it takes for the output to settle to a speci - fied level for a full - scale input change. for this device, it is specified with a 100 ? resisto r to ground. the settling time specification includes the digital delay from the sync rising edge to the full - scale output change. digital -to - analog glitch impulse the amount of charge injected from the digital in puts to the analog output when the inputs change state. this is normally specified as the area of the glitch in either picoamps per second or nanovolts per second , depending upon whether the glitch is measured as a current or voltage signal. digital feed through when the device is not selected, high frequency logic activ - ity on the devices digital inputs can be capacitively coupled through the device to show up as noise on the i out 1 and i out 2 pins and, subse quently, into the following circuitry. this noi se is digital feedthrough. multiplying feedthrough error multiplying feedthrough error is due to capacitive feedthrough from the dac reference input to the dac i out 1 line , when all 0s are loaded to the dac. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the t hd. usually only the lower - order harmonics , such as secon d to fifth , are included. 1 5 4 3 2 v v v v v thd 2 2 2 2 log 20 + + + = digital intermodulation distortion second - order intermodulation (imd) measurements are the relative magnitudes of the fa and fb tones digitally generated by the dac and the second - order products at 2fa ? fb and 2fb ? fa. compliance voltage range the maximum range of (output) terminal voltag e for which the device provides the specified characteristics. spurious - free dynamic range (sfdr) the usable dynamic range of a dac before spurious noise interferes or distorts the fundamental signal. sfdr is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full nyquist bandwidth (half the dac sampling rate or f s /2). narrow - band sfdr is a measure of sfdr over an arbitrary window size, in this case 50% of the fundamental. d igital sfdr is a measure of the usable dynamic range of the dac when the signal is a digitally generated sine wave.
data sheet ad5444/ad5446 rev. e | page 15 of 28 general description dac section the ad5444/ad5446 are 12-bit and 14-bit current output dacs consisting of segmented (4 bits), inverting rC 2r ladder configurations. a simplified diagram for the 12-bit ad5444 is shown in figure 37. 2r s1 2r s2 2r s3 2r s12 2r dac data latches and drivers r r fb i out 1 i out 2 v ref 0 4464-029 rr r figure 37. simplified ladder the feedback resistor (r fb ) has a value of r. the value of r is typically 9 k (7 k minimum, 11 k maximum). if i out 1 is kept at the same potential as gnd, a constant current flows in each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref is always constant and nomi- nally of value r. the dac output (i out 1) is code-dependent, producing various resistances and capacitances. the external amplifier choice should take into account the variation in impedance generated by the dac on the amplifiers inverting input node. access is provided to the v ref , r fb , and both i out terminals of the dac, making the device extremely versatile and allowing it to be configured in several different operating modes. for example, the device provides unipolar output mode, 4-quadrant multiplication in bipolar mode, and single-supply mode of operation. note that a matching switch is used in series with the internal r fb . power must be applied to v dd to achieve continuity when measuring r fb . circuit operation unipolar mode using a single op amp, the ad5444/ad5446 can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 38. when an output amplifier is connected in unipolar mode, the output voltage is given by ref n out v d v ??? 2 where: d is the fractional representation of the digital word loaded to the dac: d = 0 to 4095 (12-bit ad5444) d = 0 to 16383 (14-bit ad5446) n is the number of bits. note that the output voltage polarity is opposite to the v ref polarity for dc reference voltages. this dac is designed to operate with either negative or positive reference voltages. the v dd power pin is used by the internal digital logic only to drive the on and off states of the dac switches. the dac is also designed to accommodate ac refer- ence input signals in the range of ?10 v to +10 v. with a fixed +10 v reference, the circuit shown in figure 38 provides a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between digital code and expected output voltage for unipolar operation. table 5. unipolar code digital input analog output (v) 1111 1111 1111 ?v ref (4095/4096) 1000 0000 0000 ?v ref (2048/4096) = ?v ref /2 0000 0000 0001 ?v ref (1/4096) 0000 0000 0000 ?v ref (0/4096) = 0 ad5444/ ad5446 04588-030 notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf to 2pf) may be required, if a1 is a high speed amplifier. i out 1 i out 2 v ref v dd c1 a1 v out = 0v to ?v ref agnd r2 v dd v ref sdin sclk sync microcontroller r fb r1 figure 38. unipolar operation
ad5444/ad5446 data sheet rev. e | page 16 of 28 bipolar operation in some applications, it may be necessary to generate a full 4 - quadrant multiplying operation , or a bipolar output swing. this can easily be accomplished by using another external amplifier and some external resistors, as shown in figure 39. in this circuit, the second amp lifier ( a2 ) provides a gain of 2. biasing the external amplifier with an offset from the reference voltage results in a full 4 - quadrant multiplying operation. the transfer function of this circuit shows that both negative and positive output voltages are c reated as the input data ( d ) is incremented from code zero ( v out = ?v ref ) to midscale ( v out ? 0 v) to full scale ( v out = +v ref ) ref n ref out v d v v ? ? ? ? ? ? ? = ? 1 2 where: d is the fractional representation of the digital word loaded to the dac: d = 0 to 4095 (12 - bi t ad5444) d = 0 to 16383 (14 - bit ad5446) n is the resolution of the dac. when v in is an ac signal, the circuit performs 4 - quadrant multiplication. table 6 shows the relationship between digital code and the expected output volta ge for bipolar operation. table 6 . bipolar code digital input analog output (v) 1111 1111 1111 +v ref (2047/2048) 1000 0000 0000 0 0000 0000 0001 ?v ref (2047/2048) 0000 0000 0000 ?v ref (0/2048) stability in the current - to - voltage ( i - to - v ) configuration, the i out 1 of the dac and the inverting node of the op amp must be connected as closely as possible, and proper pcb layout techniques must be e mployed. because every code change corresponds to a step function, gain peaking can occur if the op amp has limited gbp and excessive parasitic capaci tance exists at the inverting node. this parasitic capaci tance introduces a pole into the open - loop respo nse that can cause ringing or instability in the closed - loop applications circuit. an optional compensation capacitor ( c1 ) can be added in parallel with r fb for stability, as shown in figure 38 and figur e 39 . too small a value for c1 can produce ringing at the output, while too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for the compensation. 04588-031 i out 1 i out 2 ad5444/ ad5446 v ref v dd c1 a1 v out = ?v ref t o +v ref agnd r2 v dd v ref 10v sdin sclk sync microcontroller a2 r4 10k? r5 20k? notes 1. r1 and r2 used on l y if gain adjustment is required. adjust r1 for v out = 0v with code 10000000 loaded t o dac. 2. m a tching and tracking is essentia l for resis t or p airs 3. c1 phase compens a tion (1pf t o 2pf) m a y be required, if a1/a2 is a high speed amplifier. r3 and r4. r3 20k? r1 r fb figure 39 . bipolar operation (4 - quadrant multiplication)
data sheet ad5444/ad5446 rev. e | page 17 of 28 single - supply applications voltage switching mode of operation figure 40 shows the ad5444/ad5446 dacs operating in the voltage switching mode. the reference voltage ( v in ) i s applied to the i out 1 pin, i out 2 is connected to agnd, and the output voltage is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage, making single - supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance). therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance but rather one that varies with code, so the voltage input should be driven from a low impedance source. 04588-032 notes 1. additiona l pins omitted for clarit y . 2. c1 phase compens a tion (1pf t o 2pf) m a y be required, if a1 is a high speed amplifier. i out 1 gnd v out r2 v in r fb v dd v ref r1 v dd figure 40 . single - supply voltage switching mode operation it is important to note that, with this configuration, v in is lim - ited to low voltages, because the switches in the dac ladder do not have the same source - drain drive voltage. as a result, their on resistance differs, which degrades the integral linearity of the dac. in addition, v in must not go negative by more than 0.3 v, or an internal diode turns on, exceeding the maxi mum ratings of the device. in this type of application, the full range of the multiplying capability of the dac is lost. positive output voltage the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive v oltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistors tolerance errors. to generate a negative reference, the reference can be level - shifted by a n op amp such that the v out and gnd pins of the reference become the virtual ground and ?2.5 v, respectively, as shown in figure 41. v dd r fb i out 1 i out 2 c1 v out = 0v t o +2.5v gnd v dd = +5v v ref notes 1. additiona l pins omitted for clarit y . 2. c1 phase compens a tion (1pf t o 2pf) m a y be required, if a1 is a high speed amplifier. adr03 v out v in gnd ?5v +5v ?2.5v 04588-033 figure 41 . positive voltage output with minimum components adding ga in in applications in which the output voltage is required to be greater than v in , gain can be added with an additional external amplifier, or it can be achieved in a single stage. it is important to take into consideration the effect of the temperature co effi - cients of the dacs thin film resistors. simply placing a resistor in series with the r fb resistor can cause mismatches in the temperature coefficients and result in larger gain temperature coefficient errors. instead, increase the gain of the circuit by using the recommended configuration shown in figure 42. r1, r2, and r3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuit s where gains of greater than 1 are required. notes 1. additiona l pins omitted for clarit y . 2. c1 phase compens a tion (1pf t o 2pf) m a y be required, if a1 is a high speed amplifier. v dd r fb i out 1 i out 2 c1 v out gnd v dd v ref 04588-034 gain = r1 = r2 + r3 r2 r2r3 r2 + r3 r1 v in r3 r2 figure 42 . increasing gain of current output dac divider or programma ble gain element current - steering dacs are very flexible and lend themselves to many different applications. if th is type of dac is connected as the feedback element of an op amp and r fb is used as the input resistor, as shown in figure 43 , then the output voltage is inversely proportional to the digital input fraction, d . for d = 1 ? 2 ? n , the output voltage is v out = ?v in / d = ?v in /(1 ? 2 ? n )
ad5444/ad5446 data sheet rev. e | page 18 of 28 04588-035 notes: 1. additiona l pins omitted for clarit y . i out 1 gnd v out v in r fb v dd v ref v dd figure 43 . current - steering dac used as a divider or programmable gain element as d is reduced, the output voltage increases. for small values of the digital fraction ( d ) , it is important to ensure that the amplifier does not saturate and the required accuracy is met. for example, an 8 - bit dac driven with the binary code 0x10 (0001 0000), that is, 16 decimal, in the circuit of figure 43, should cause the output voltage to be 16 v in . however, if the dac has a linearity specification of 0.5 lsb, then d can, in fact, have a weight in the range of 15.5/256 to 16.5/256, so the possible output voltage is in the range 15.5 v in to 16.5 v in . this is an error of 3%, even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. because o nly a fraction ( d ) of the current into the v ref terminal is routed to the i out 1 terminal, the output voltage has to change, as follows: output error voltage d ue to dac leakage = ( leakage r )/ d where r is the dac resistance at the v ref terminal. for a dac leakage current of 10 na, r equal to 10 k?, and a ga in (1/ d ) of 16, the error voltage is 1.6 mv. amplifier selection the primary requirement for the current - steering mode is an amplifier with low input bias currents and low input offset voltage. the input offset voltage of an op amp is multiplied by the variable gain (due to the code - dependent output resistance of the dac) of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the dac to be nonmonotonic. the in put bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent any significant errors in 12- bit applications. common - mode rejection of the op amp is importan t in voltage switching circuits because it produces a code - dependent error at the voltage output of the circuit. most op amps have adequate common - mode rejection for use at 8 - bit, 10 - bit, and 12 - bit resolution s. provided that the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. conse quently, the slew rate and settling time of a voltage switchi ng dac circuit is dete rmined largely by the output op amp. to obtai n minimum settling time in this configuration, it is impor - tant to minimize capacitance at the v ref node (voltage output node in this application) of the dac. this is done by using low input, capacitance buffer amplifiers and careful board design. most s ingle - supply circuits inclu de ground as part of the analog sign al range, which, in turn, requires an amplifier that can han dle rail - to - rail signals. a large ran ge of single - supply amplifiers is available from analog devices , inc. (see table 8 and table 9 for suitable suggestions). reference selection when selecting a reference for use with the ad5444/ad5446 current output dac, pay attention to the output voltage tem - perature coefficient specification. thi s parameter affects not only the full - scale error but can also affect the linearity (inl and dnl) performance. the reference temperature coefficient should be consistent with the system accuracy specifications. for example, an 8 - bit system required to hold its overall speci - fication to within 1 lsb over the temperature range 0c to 50c dictates that the maximum system drift with temperature should be less than 78 ppm/c. a 12- bit system with the same temperature range to overall specification within 2 lsb s requires a maximum drift of 10 ppm/c. by choosing a precision reference with low output temperature coefficient, this error source can be minimized. table 7 suggests some of the dc references available from analog devices that are suitable for use with this range of current output dacs.
data sheet ad5444/ad5446 rev. e | page 19 of 28 table 7 . suitable a nalog d evices precision references part no. output voltage (v) initial tolerance accuracy ( %) temp erature drift coefficient (ppm/c) i ss (ma) output noise (v p - p) package adr01 10 0.05 3 1 20 soic -8 adr01 10 0.05 9 1 20 tsot - 23, sc70 adr02 5 0.06 3 1 10 soic -8 adr02 5 0.06 9 1 10 tsot - 23, sc70 adr03 2.5 0.10 3 1 6 soic -8 adr03 2.5 0.10 9 1 6 tsot - 23, sc70 adr06 3 0.10 3 1 10 soic -8 adr06 3 0.1 0 9 1 10 tsot - 23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic -8 ADR435 5 0.04 3 0.8 8 soic -8 adr391 2.5 0.16 9 0.12 5 tsot -23 adr395 5 0.10 9 0.12 8 tsot -23 table 8 . suitable analog devices precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0 .1 hz to 10 hz noise (v p - p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic -8 op1177 2.5 to 15 60 2 0.4 500 msop, soic - 8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic - 8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic -8 table 9 . suitable a nalog d evices high speed op amps part no. supply voltage (v) bw @ acl (typ) (mhz) slew rate (typ) (v/s) v os (max) (v) i b (max) (n a) package ad8065 5 to 24 145 180 1500 0.006 soic - 8, sot - 23, msop ad8021 2. 2 5 to 12 490 120 1000 10500 soic - 8, msop ad8038 3 to 12 350 425 3000 750 soic - 8, sc70-5 ad9631 3 to 6 320 1300 10, 000 7000 soic -8
ad5444/ad5446 data sheet rev. e | page 20 of 28 serial interface the ad5444/ad5446 hav e an easy - to - use , 3 - wire interface that is compatible with spi, qspi, microwire, and dsp inter - face standards. data is written to the device in 16 - bit words. this 16 - bit word consists of two control bit s, 12 data bits or 14 data bits, as shown in figure 44 and figure 45 . the ad5446 uses all 14 bits of dac data while ad5444 uses 12 bits and ignores the 2 lsbs. control bit c1 and control bit c0 allow the user to load and update the new dac code and to ch ange the active clock edge. by default, the shift register clocks data on the falling edge, but this can be changed via the control bits. if changed, the dac core is inop erative until the next data frame. a power cycle resets this back to the default cond ition. on - chip, power - on reset circuitry ensures the device powers on with zero scale loaded to the dac register and the i out line. table 10 . dac control bits c1 c0 function implemented 0 0 load and update (power - on default) 0 1 disable sdo 1 0 no operation 1 1 clock data to shift register on rising edge sync function sync is an edge - triggered input that acts as a frame synchroni - za tion signal. data can be transferred in to the device only while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync falling to the sclk falling edge setup time, t 4 . to minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . the sclk and din input buffers are powered down on the rising edge of sync . after the falling edge of the 16th sclk pulse, bring sync high to transfer data from the input shift register to the dac register. daisy - chain mode daisy - chain mode is the default power - on mode. to disable the daisy - ch ain function, write 01 to the control word. in daisy - chain mode, the internal gating on the sclk is disabled. the sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, th e data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of the sclk (this is the default; use the control word to change the active edge) and is valid for the next device on the falling edge (defau lt). by connecting this line to the sdin input on the next device in the chain, a multidevice interface is constructed. sixteen clock pulses are required for each device in the system. therefore, the total number of clock cycles must equal 16 n , where n i s the number of devices in the chain. when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data from being clocked into the shift register. a burst clock containing the exact numb er of clock cycles can be used, and sync can be taken high some time later. after the rising edge of sync , data is automatically transferred from each devices input register to the addressed dac. when the con trol bits = 10, the device is in no operation mode. this can be useful in daisy - chain applications where the user does not want to change the settings of a particular dac in the chain. simply write 10 to the control bits for that dac and the following data bits are ignored. 04588-037 db0 (lsb) db15 (msb) db7 db6 db5 db4 db3 db2 db0 db1 c1 c0 db11 db10 db8 db9 x x control bits data bits figure 44 . ad5444 12 - bit input shift register contents 04588-038 db0 (lsb) db15 (msb) db9 db8 db7 db6 db5 db4 db2 db3 c1 c0 db13 db12 db10 db 1 1 db0 db1 contro l bits d at a bits figure 45 . ad5446 14 - bit input shift register contents
data sheet ad5444/ad5446 rev. e | page 21 of 28 microprocessor interfacing microprocessor interfacing to the ad5444/ad5446 dac is through a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communica- tions channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5444/ad5446 requires a 16-bit word, with the default being data valid on the falling edge of sclk, but this can be changed using the control bits in the data-word. adsp-21xx to ad5444/ad5446 interface the adsp-21xx family of dsps is easily interfaced to the ad5444/ad5446 dac without the need for extra glue logic. figure 46 is an example of an spi interface between the dac and the adsp-2191m. sck of the dsp drives the serial clock line, sclk. sync is driven from one of the port lines, in this case spixsel . sclk sck sync spixsel sdin mosi adsp-2191m* *additional pins omitted for clarity. ad5444/ ad5446* 04588-074 figure 46. adsp-2191m spi to ad5444/ad5446 interface a serial interface between the dac and dsp sport is shown in figure 47. in this interface example, sport0 is used to trans- fer data to the dac shift register. transmission is initiated by writing a word to the tx register after the sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsp serial clock and clocked into the dac input shift register on the falling edge of its sclk. the update of the dac output takes place on the rising edge of the sync signal. sclk sclk sync tfs sdin dt adsp-2101/ adsp-2191m* *additional pins omitted for clarity. 04588-082 ad5444/ad5446* figure 47. adsp-2101/adsp-2191m to ad5444/ad5446 interface communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and sclk width. the dac inter- face expects a t 4 ( sync falling edge to sclk falling edge setup time) of 13 ns minimum. see the adsp-21xx user manual for information on clock and frame sync frequencies for the sport register. table 11 shows the setup for the sport control register. table 11. sport control register setup name setting description tfsw 1 alternate framing invtfs 1 active low frame signal dtype 00 right-justify data isclk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 1111 16-bit data-word adsp-bf5xx to ad5444/ad5446 interface the adsp-bf5xx family of processors has an spi-compatible port that enables the processor to communicate with spi- compatible devices. a serial interface between the adsp-bf5xx and the ad5444/ad5446 dac is shown in figure 48. in this configuration, data is transferred through the mosi (master output/slave input) pin. sync is driven by the spi chip select pin, which is a reconfigured programmable flag pin. sclk sck sync spixsel sdin mosi adsp-bf5xx* *additional pins omitted for clarity ad5444/ad5446* 04588-039 figure 48. adsp-bf5xx to ad5444/ad5446 interface the adsp-bf5xx processor incorporates channel synchronous serial ports (sport). a serial interface between the dac and the dsp sport is shown in figure 49. when the sport is enabled, initiate transmission by writing a word to the tx register. the data is clocked out on each rising edge of the dsps serial clock and clocked into the dac input shift register on the falling edge of its sclk. the dac output is updated by using the transmit frame synchronization (tfs) line to provide a sync signal. sclk sclk sync tfs sdin dt adsp-bf5xx* *additional pins omitted for clarity 04588-040 ad5444/ad5446* figure 49. adsp-bf5xx to ad5444/ad5446 interface
ad5444/ad5446 data sheet rev. e | page 22 of 28 80c51/80l51 to ad5444/ad5446 interface a serial interface between the dac and the 80c51/80l51 is shown in figure 50 . txd of the 80c51/80l51 drives sclk of the dac serial interface, while rxd drives the serial data li ne, sdin. p1.1 is a bit - programmable pin on the serial port and is used to drive sync . when data is to be transmitted to the switch, p1.1 is taken low. the 80c51/80l51 transmits data only in 8 - bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data correctly to the dac, p1.1 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. data on rxd is clocked out of the microcon troller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between the dac and microcontroller inter - face. p1.1 is taken high following the completion of this cycle. the 80c51/80l51 provides the lsb of its sb uf register as the first bit in the data stream. the dac input register requires its data with the msb as the first bit received. the transmit routine should take this into account. sclk txd 8051* sync p1.1 sdin rxd *additiona l pins omitted for clarit y 04588-041 ad5444/ad5446* figure 50 . 80c51/80l51 to ad5444/ad5446 interf ace mc68hc11 interface to ad5444/ad5446 interface figure 51 is an example of a serial interface between the dac and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mod e (mstr) = 1, clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr); see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the dac interface, the mosi output drives the serial d ata line (sdin) of the ad5444/ ad5446. the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5444/ad5446, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the dac, pc7 is left low after t he first eight bits are tra nsferred, and a second serial write operation is perfor med to the dac. pc7 is taken high at the end of this procedure. sclk sck ad5444/ad5446* sync pc7 sdin mosi mc68hc 1 1* *additiona l pins omitted for clarit y 04588-042 figure 51 . mc 68hc11 to ad5444/ad5446 interface if the user wants to verify the dat a previously written to the input shift register, the sdo line can be connected to miso of the mc68hc11, and, with sync low, the shift register clocks data out on the rising edges of sclk. microwire to ad5444/ad5446 interface figure 52 shows an interface between the dac and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the dac input shift register on the rising edge of sk, which c orresponds to the falling edge of the dac sclk. sclk sk microwire* sync cs sdin so *additiona l pins omitted for clarit y 04588-043 ad5444/ad5446* figure 52 . microwire to ad5444 /ad5446 interface pic16c6x/7x to ad5444/ad5446 interface the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock p olarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon); see the pic16/17 microcontroller user manual . in this example, i/o port ra1 is used to provide a sync signal and enable the se rial port of the dac. this micro - controller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. figure 53 shows the connection diagram. sclk sck/rc3 pic16c6x/7x* sync ra1 sdin sdi/rc4 *additiona l pins omitted for clarit y 04588-044 ad5444/ad5446* figure 53 . pic16c6x/7x to ad5444/ad5446 interface
data sheet ad5444/ad5446 rev. e | page 23 of 28 pcb layout and power supply decoupling in any circuit where accuracy is important, careful considera - tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit boards on which the ad5444/ad5446 are mounted should be designed so the analog and digital sections are separated and confined to certain areas of the board. if the dacs are in systems in w hich multiple devices require a agnd - to - dgnd co nnection, the connection should be made at one point only. the star ground point should be established as close as possible to the devices. the dac should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the pa ck - age as possible, ideally right up against the device. the 0.1 f capaci tor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high freque ncies, to handle transient currents due to internal logic switching. low esr, 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. fast switching sig nals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on oppo - site sides of the board should run at right angles to each other. this reduces the effects of feedthrough through out the board. a microstrip technique, by far the best, is not always possible with a double - sided board. in this technique, the component side of the board is dedicated t o the ground plane, while signal traces are placed on the solder side. it is good practice to employ compact, minimum lead - length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize high frequency performance, the i - to - v amplifier should be located as close to the device as possible.
ad5444/ad5446 data sheet rev. e | page 24 of 28 overview of ad54 xx and ad55 xx current output devices table 12. part n umber resolution (bits) number of dacs inl (lsb) interface package 1 features ad5424 8 1 0.25 parallel ru - 16, cp -20 10 mhz bw, 17 ns cs pulse w idth ad5426 8 1 0.25 serial rm - 10 10 mhz bw, 50 mhz s er ial ad5428 8 2 0.25 parallel ru -20 10 mhz bw, 17 ns cs pulse w idth ad5429 8 2 0.25 serial ru -10 10 mhz bw, 50 mhz s erial ad5450 8 1 0.25 serial uj -8 12 mhz bw, 50 mhz s erial ad5432 10 1 0.5 serial rm - 10 10 mhz bw, 50 mhz s erial ad5433 10 1 0.5 parallel ru - 20, cp -20 10 mhz bw, 17 ns cs p ulse w idth ad5439 10 2 0.5 serial ru - 16 10 mhz bw, 50 mhz s erial ad5440 10 2 0.5 parallel ru -24 10 mhz bw, 17 ns cs p ulse w idth ad5451 10 1 0.25 serial uj -8 12 mhz bw, 50 mhz s erial ad5443 12 1 1 serial rm - 10 10 mhz bw, 50 mhz s erial ad5444 12 1 0.5 serial rm - 10 12 mhz bw, 50 mhz s erial i nterface ad5415 12 2 1 serial ru -24 10 mhz bw, 50 mhz s erial ad5405 12 2 1 parallel cp -40 10 mhz bw, 17 ns cs p ulse w idth ad5445 12 2 1 parallel ru - 20, cp -20 10 mhz bw, 17 ns cs p ulse w idth ad5447 12 2 1 parallel ru -24 10 mhz bw, 17 ns cs p ulse w idth ad5449 12 2 1 serial ru -16 10 mhz bw, 50 mhz s erial ad5452 12 1 0.5 serial uj - 8, rm -8 12 mhz bw, 50 mhz s erial ad5446 14 1 1 serial rm - 10 12 mhz bw, 50 mhz s erial ad5453 14 1 2 serial uj - 8, rm -8 12 mhz bw, 50 mhz s erial ad5553 14 1 1 serial rm - 8 4 mhz bw, 50 mhz s erial c lock ad5556 14 1 1 parallel ru -28 4 mhz bw, 20 ns wr p ulse w idth ad5555 14 2 1 serial rm - 8 4 mhz bw, 50 mhz s erial c lock ad5557 14 2 1 parallel ru -38 4 mhz bw, 20 ns wr p ulse w idth ad55 43 16 1 2 serial rm - 8 4 mhz bw, 50 mhz serial c lock ad5546 16 1 2 parallel ru -28 4 mhz bw, 20 ns wr pulse w idth ad5545 16 2 2 serial ru -16 4 mhz bw, 50 mhz serial c lock ad5547 16 2 2 parallel ru -38 4 mhz bw, 20 ns wr pulse w idth 1 ru = tssop, cp = lfcsp, rm = msop, uj = tsot.
data sheet ad5444/ad5446 rev. e | page 25 of 28 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanar ity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 54 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model 1 resolution (bits) inl (lsb) temperature range package description packag e option branding ad5444yrm 12 0.5 ?40c to +125c 10- lead msop rm - 10 d27 ad5444yrm - reel 12 0.5 ?40c to +125c 10- lead msop rm - 10 d27 ad5444yrm - reel7 12 0.5 ?40c to +125c 10- lead msop rm - 10 d27 ad5444yrmz 12 0.5 ?40c to +125c 10- lead msop rm - 10 d6x ad5444yrmz - ree l 12 0.5 ?40c to +125c 10- lead msop rm - 10 d6x ad5444yrmz - reel7 12 0.5 ?40c to +125c 10- lead msop rm - 10 d6x ad5446yrm 14 2 ?40c to +125c 10- lead msop rm - 10 d28 ad5446yrm - reel 14 2 ?40c to +125c 10- lead msop rm - 10 d28 ad5446yrm -r eel7 14 2 ?40c to +125c 10- lead msop rm - 10 d28 ad5446yrm z 14 2 ?40c to +125c 10- lead msop rm - 10 d7z ad5446yrmz - rl7 14 2 ?40c to +125c 10- lead msop rm - 10 d7z ev - ad5443/46/53sdz evaluation board 1 z = rohs compliant part.
ad5444/ad5446 data sheet rev. e | page 26 of 28 notes
data sheet ad5444/ad5446 rev. e | page 27 of 28 notes
ad5444/ad5446 data sheet rev. e | page 28 of 28 notes ? 2004 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04588 - 0 - 6/13(e)

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